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ISL6742
Data Sheet October 31, 2008 FN9183.2
Advanced Double-Ended PWM Controller
The ISL6742 is a high-performance double-ended PWM controller with advanced synchronous rectifier control and current limit features. It is suitable for both current- and voltage-mode control methods. The ISL6742 includes complemented PWM outputs for synchronous rectifier (SR) control. The complemented outputs may be dynamically advanced or delayed relative to the main outputs using an external control voltage. Its advanced current sensing circuitry employs sample and hold methods to provide a precise average current signal. Suitable for average current limiting, a technique which virtually eliminates the current tail-out common to peak current limiting methods, it is also applicable to current sharing circuits and average current mode control. This advanced BiCMOS design features an adjustable oscillator frequency up to 2MHz, internal over-temperature protection, precision deadtime control, and short propagation delays. Additionally, Multi-Pulse Suppression ensures alternating output pulses at low duty cycles where pulse skipping may occur.
Features
* Synchronous Rectifier Control Outputs with Adjustable Delay/Advance * Adjustable Average Current Signal * 3% Tolerance Cycle-by-Cycle Peak Current Limit * Fast Current Sense to Output Delay * Adjustable Oscillator Frequency Up to 2MHz * Adjustable Deadtime Control * Voltage- or Current-Mode Operation * Separate RAMP and CS Inputs for Voltage Feed-Forward or Current-Mode Applications * Tight Tolerance Error Amplifier Reference Over Line, Load, and Temperature * 175A Start-up Current * Supply UVLO * Adjustable Soft-Start * 70ns Leading Edge Blanking * Multi-Pulse Suppression
Ordering Information
PART NUMBER (Note) PART MARKING TEMP. RANGE PACKAGE (C) (Pb-free) -40 to +105 PKG. DWG. #
* Internal Over-Temperature Protection * Pb-Free (RoHS Compliant)
ISL6742AAZA* ISL 6742AAZ
16 Ld QSOP M16.15A
Applications
* Half-Bridge, Full-Bridge, Interleaved Forward, and Push-Pull Converters * Telecom and Datacom Power * Wireless Base Station Power * File Server Power * Industrial Power Systems
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL6742 (16 LD QSOP) TOP VIEW
VREF 1 VERR 2 RTD 3 CT 4 FB 5 RAMP 6 CS 7 IOUT 8 16 SS 15 VADJ 14 VDD 13 OUTA 12 OUTB 11 OUTAN 10 OUTBN 9 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VDD OUTA VDD VREF UVLO PWM STEERING LOGIC DELAY/ ADVANCE TIMING CONTROL OUTB
2
OVERTEMPERATURE PROTECTION GND VREF IOUT 4X SAMPLE AND HOLD CT OSCILLATOR RTD VREF SS
FN9183.2 October 31, 2008
OUTAN OUTBN VADJ
+ 1.00V +70ns LEADING EDGE BLANKING
CS
OVERCURRENT COMPARATOR
ISL6742
RAMP PWM COMPARATOR + 0.33 VERR VREF 80mV 1 mA
SOFT-START CONTROL
+ -
0.6V FB
Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification
VIN+ Q1 C2 T1 C15 R16 Q3 Q5 C16
L1 + C22 C23
+VOUT
RTN
R13 C1 T2 Q4 R17 R15 R25 T3 CR4 U6 C3 C7 CR1 U1 HIP2100 C4
VDD LO HB VSS HO LI HS HI
3
R1 CR 3 36V TO 75V Q2 C14 C5 VINR3 R2 R5 Q7 C8 VR1 C6 R4
FN9183.2 October 31, 2008
Q6
C17 R9
EL7212
C18
EL7212
U5
CR2
R8 R7
R14
C24
ISL6742
+VOUT U2 ISL6742 C13 1 2 3 4 5 6 7 8 VREF VERR RTD CT SS 16 VADJ 15 VDD 14 OUTA 13 R19 R22 R23 R20 C19 R18 C20
OUTB 12 FB RAMP OUTAN 11 OUTBN 10 CS IOUT GND 9 R11
R6
R21
C21
R10 C9 C10 C11 R12
C12
U3 VR 2 U4 TL431 R24
Typical Application - High Voltage Input Secondary Side Control Full-Bridge Converter
VIN+ Q1 Q5A Q5B R13 CR4 T3 C9 CR3 R14 C10 T1 Q6A Q6B Q2
4
R15 Q16 + 400 VDC C11 C1 R17 C18 Q15 Q4 Q7A Q7B R12 CR6 CR5 R11 C8 C7 Q8A Q8B Q3 Q11A Q11B C6 Q12A Q12B VINT2 Q15 CR1 CR2 R6 R9 R21 C12 R7 VREF 1 2 3 4 5 6 7 8 VREF VERR RTD CT FB RAMP CS IOUT SS 16 VADJ15 VDD14 OUTA13 OUTB12 OUTAN11 OUTBN 10 GND 9 R10 Q13A Q13B ISL6742 Q14A Q14B R8 U1 R4 SECONDARY BIAS SUPPLY C2 R2
FN9183.2 October 31, 2008
R16 L1 C19 C20 C21 + + VOUT
RETURN
ISL6742
R20 C17 C16
R18
C3 C13 C4 R5 R3 C5 C14 C15 VREF R22 R23
CR7 + U3 C22 R19
ISL6742
Absolute Maximum Ratings (Note 2)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUTxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
Thermal Information
Thermal Resistance Junction to Ambient (Typical) JA (C/W) 16 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C Supply Voltage Range (Typical). . . . . . . . . . . . . . . 9VDC to 16 VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2, "Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification" on page 3 and "Typical Application - High Voltage Input Secondary Side Control Full-Bridge Converter" on page 4. 9V < VDD < 20V, RTD = 10.0k, CT = 470pF, TA = -40C to +105C, Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VOLTAGE Supply Voltage Start-Up Current, IDD Operating Current, IDD UVLO START Threshold UVLO STOP Threshold Hysteresis REFERENCE VOLTAGE Overall Accuracy Long Term Stability Operational Current (Source) Operational Current (Sink) Current Limit CURRENT SENSE Current Limit Threshold CS to OUT Delay Leading Edge Blanking (LEB) Duration CS to OUT Delay + LEB CS Sink Current Device Impedance Input Bias Current IOUT Sample and Hold Buffer Amplifier Gain IOUT Sample and Hold VOH IOUT Sample and Hold VOL
VDD = 5.0V RLOAD, COUT = 0 8.00 6.50 -
175 7.5 8.75 7.00 1.75
20 400 12.0 9.00 7.50 -
V A mA V V V
IVREF = 0mA to 10mA TA = +125C, 1000 hours (Note 3)
4.850 -10 5
5.000 3 -
5.150 -100
V mV mA mA mA
VREF = 4.85V
-15
VERR = VREF Excl. LEB (Note 3) (Note 3) TA = +25C VCS = 1.1V VCS = 0.3V TA = +25C VCS = 1.00V, ILOAD = -300A VCS = 0.00V, ILOAD = 10A
0.97 50 -1.0 4.00 3.9 -
1.00 35 70 4.09 -
1.03 50 100 130 20 1.0 4.15 0.3
V ns ns ns A V/V V V
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ISL6742
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2, "Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification" on page 3 and "Typical Application - High Voltage Input Secondary Side Control Full-Bridge Converter" on page 4. 9V < VDD < 20V, RTD = 10.0k, CT = 470pF, TA = -40C to +105C, Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER RAMP RAMP Sink Current Device Impedance RAMP to PWM Comparator Offset Bias Current Clamp Voltage SOFT-START Charging Current SS Clamp Voltage SS Discharge Current Reset Threshold Voltage ERROR AMPLIFIER Input Common Mode (CM) Range GBWP VERR VOL VERR VOH VERR Pull-Up Current Source EA Reference EA Reference + EA Input Offset Voltage PULSE WIDTH MODULATOR Minimum Duty Cycle Maximum Duty Cycle (Per Half-cycle) (Note 3) (Note 3) SS = 2V SS = 3V
VRAMP = 1.1V TA = +25C VRAMP = 0.3V (Note 3)
65 -5.0 6.5
80 -
20 95 -2.0 8.0
mV A V
-60 4.410 10 0.23
-70 4.500 0.27
-80 4.590 0.33
A V mA V
TA = +25C
0 5 4.20 0.8 0.594 0.590
1.0 0.600 0.600
VREF 0.4 1.3 0.606 0.612
V MHz V V mA V V
ILOAD = 2mA ILOAD = 0mA VERR = 2.50V TA = +25C
VERR < 0.6V VERR = 4.20V, VRAMP = 0V, VCS = 0V (Note 4) RTD = 2.00k, CT = 220pF RTD = 2.00k, CT = 470pF
0.85
94 97 99 0.8 0.33 -
0 1.20 0.9 0.35 4.45
% % % % V V V/V V
Zero Duty Cycle VERR Voltage VERR to PWM Comparator Input Offset VERR to PWM Comparator Input Gain Common Mode (CM) Input Range OSCILLATOR Frequency Accuracy, Overall (Note 3) (Note 3) TA = +25C
0.7 0.31 0
165 -10
183 0.3 4.5 1.5 -200 21
201 +10 1.7 -207 23
kHz % % % % A A/A
Frequency Variation with VDD Temperature Stability
TA = +25C, (F20V- - F10V)/F10V VDD = 10V, |F-40C - F0C|/F0C (Note 3) |F0C - F105C|/F25C (Note 3)
-193 19
Charge Current Discharge Current Gain
TA = +25C, VCS = 1.8V
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ISL6742
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2, "Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification" on page 3 and "Typical Application - High Voltage Input Secondary Side Control Full-Bridge Converter" on page 4. 9V < VDD < 20V, RTD = 10.0k, CT = 470pF, TA = -40C to +105C, Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEST CONDITIONS Static Threshold Static Threshold Static Value MIN 0.75 2.75 1.92 1.97 TYP 0.80 2.80 2.00 2.00 MAX 0.88 2.88 2.05 2.03 UNITS V V V V
PARAMETER CT Valley Voltage CT Peak Voltage CT Pk-Pk Voltage RTD Voltage OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Rise Time Fall Time UVLO Output Voltage Clamp Output Delay/Advance Range OUTAN/OUTBN Relative to OUTA/OUTB
IOUT = -10mA, VDD - VOH IOUT = 10mA, VOL - GND COUT = 220pF, VDD = 15V (Note 3) COUT = 220pF, VDD = 15V (Note 3) VDD = 7V, ILOAD = 1mA (Note 5) VADJ = 2.50V (Note 3) VADJ < 2.425V VADJ > 2.575V
-40 40 2.575 0
0.5 0.5 110 90 -
1.0 1.0 200 150 1.25 3 -300 300 5.000 2.425
V V ns ns V ns ns ns V V
Delay Control Voltage Range OUTAN/OUTBN Relative to OUTA/OUTB VADJ Delay Time
OUTxN Delayed OUTx Delayed TA = +25C (OUTx Delayed) (Note 6) VADJ = 0 VADJ = 0.5V VADJ = 1.0V VADJ = 1.5V VADJ = 2.0V TA = +25C (OUTxN Delayed) VADJ = VREF VADJ = VREF - 0.5V VADJ = VREF - 1.0V VADJ = VREF - 1.5V VADJ = VREF - 2.0V
280 92 61 48 41
300 105 70 55 50
320 118 80 65 58
ns ns ns ns ns
280 86 59 47 41
300 100 68 55 48
320 114 77 62 55
ns ns ns ns ns
THERMAL PROTECTION Thermal Shutdown Thermal Shutdown Clear Hysteresis, Internal Protection NOTES: 3. Limits established by characterization and are not production tested. 4. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using other values for these components. See Equations 1 through 3. 5. Adjust VDD below the UVLO stop threshold prior to setting at 7V. 6. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time (deadtime) as determined by CT and RTD. (Note 3) (Note 3) (Note 3) 130 115 140 125 15 150 135 C C C
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ISL6742 Typical Performance Curves
1.02 CT DISCHARGE CURRENT GAIN 25 24 23 22 21 20 19 18 -25 -10 5 20 35 50 65 80 95 110 0 200 400 600 800 1000 TEMPERATURE (C) RTD CURRENT (A)
NORMALIZED VREF
1.01
1.00
0.99
0.98 -40
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
1*104
1*103
1*103 CT = 1000pF 680pF 470pF 330pF 220pF 100pF 0 10 20 30 40 50 60 RTD (k) 70 80 90 100
FREQUENCY (kHz)
DEADTIME (ns)
100
100
10
10 0.1
RTD= 10k 50k 100k 1 CT (nF) 10
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a 0.1F or larger high frequency ceramic capacitor as close to the VDD and GND pins as possible. VDD is monitored for supply voltage undervoltage lock-out (UVLO). The start and stop thresholds track each other resulting in relatively constant hysteresis. GND - Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. VREF - The 5V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a 0.1F to 2.2F low ESR capacitor. CT - The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200A current source and discharged with a user adjustable current source controlled by RTD.
RTD - This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this pin and GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the resistor current. The PWM deadtime is determined by the timing capacitor discharge duration. The voltage at RTD is nominally 2V. The minimum recommended value of RTD is 2.00k. CS - This is the input to the overcurrent comparator and the average current sample and hold circuit. The overcurrent comparator threshold is set at 1V nominal. The CS pin is shorted to GND at the termination of either PWM output. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. This delay may result in CS being discharged prior to the power switching device being turned off. OUTA and OUTB - These paired outputs are the pulse width modulated outputs for controlling the switching FETs in alternate sequence.
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OUTAN and OUTBN - These outputs are the complements of OUTA and OUTB, respectively. These outputs are suitable for control of synchronous rectifiers. The phase relationship between each output and its complement is set by a control voltage applied to VADJ. VADJ - A 0V to 5V control voltage applied to this input sets the relative delay or advance between OUTA/OUTB and OUTAN/OUTBN. Voltages below 2.425V result in OUTAN/OUTBN being advanced relative to OUTA/OUTB. Voltages above 2.575V result in OUTAN/OUTBN being delayed relative to OUTA/OUTB. A voltage of 2.50V 75mV results in zero phase difference. A weak internal 50% divider from VREF results in no phase delay if this input is left floating. The range of phase delay/advance is either zero or 40ns to 300ns with the phase differential increasing as the voltage deviation from 2.5V increases. The relationship between the control voltage and phase differential is non-linear. The gain (t/V) is low for control voltages near 2.5V and rapidly increases as the voltage approaches the extremes of the control range. This behavior provides the designer increased accuracy when selecting a shorter delay/advance duration. When the PWM outputs are delayed relative to the SR outputs (VADJ < 2.425V), the delay time should not exceed 90% of the deadtime as determined by RTD and CT. IOUT - Output of the 4x buffer amplifier of the sample and hold circuitry that captures and averages the CS signal. RAMP - This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected directly to CS and the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate an appropriate signal, or RAMP may be connected to the input voltage through an RC network for voltage feed forward control, or RAMP may be connected to VREF through an RC network to produce the desired sawtooth waveform. FB - FB is the inverting input to the error amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or used as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded. VERR - The VERR pin is the output of the error amplifier and controls the inverting input of the PWM comparator. Feedback compensation components connect between VERR and FB. There is a nominal 1mA pull-up current source connected to VERR. Soft-start is implemented as a voltage clamp on the VERR signal. The outputs, OUTA and OUTB, reduce to 0% duty cycle when VERR is pulled below 0.6V. OUTAN and OUTBN, the complements of OUTA and OUTB, respectively, go to 100% duty cycle when this occurs. SS - Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor determines the rate of increase of the duty cycle during start-up. Although no minimum value of capacitance is required, it is recommended that a value of at least 100pF be used for noise immunity. SS may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration.
Functional Description
Features
The ISL6742 PWM is an excellent choice for low cost bridge and push-pull topologies in applications requiring accurate duty cycle and deadtime control. With its many protection and control features, a highly flexible design with minimal external components is possible. Among its many features are current- or voltage-mode control, adjustable soft-start, peak and average overcurrent protection, thermal protection, synchronous rectifier outputs with variable delay/advance timing, and adjustable oscillator frequency.
Oscillator
The ISL6742 oscillator, with a programmable frequency range to 2MHz, is set with only an external resistor and capacitor. The switching period is the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and a fixed 200A internal current source. The discharge duration is determined by RTD and CT.
t C 11.5 10 CT
3
S
-9
(EQ. 1)
t D ( 0.06 RTD CT ) + 50 10 1 t SW = t C + t D = ----------F SW
S
(EQ. 2)
S
(EQ. 3)
where tC and tD are the charge and discharge times, respectively, tSW is the oscillator period, and FSW is the oscillator frequency. Since the ISL6742 is a double-ended controller, one output switching cycle requires two oscillator cycles. The actual charge and discharge times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. This delay adds directly to the switching duration, but also causes slight overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low discharge currents are used, there will be increased error due to the input impedance at the CT pin.
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The maximum duty cycle, D, and percent deadtime, DT, can be calculated from:
tC D = --------t SW DT = 1 - D (EQ. 4)
(EQ. 5)
The current sense signal applied to the CS pin connects to the peak current comparator and a sample and hold averaging circuit. After a 70ns leading edge blanking (LEB) delay, the current sense signal is actively sampled during the on-time, the average current for the cycle is determined, and the result is amplified by 4x and output on the IOUT pin. If an RC filter is placed on the CS input, its time constant should not exceed ~50ns or significant error may be introduced on IOUT.
Soft-Start Operation
The ISL6742 features a soft-start using an external capacitor in conjunction with an internal current source. Soft-start reduces component stresses and surge currents during start-up. Upon start-up, the soft-start circuitry limits the error voltage input (VERR) to a value equal to the soft-start voltage. The output pulse width increases as the soft-start capacitor voltage increases. This has the effect of increasing the duty cycle from zero to the regulation pulse width during the soft-start period. When the soft-start voltage exceeds the error voltage, softstart is completed. Soft-start occurs during start-up and after recovery from a fault condition. The soft-start charging period may be calculated using Equation 6:
t = 64.3 C ms (EQ. 6)
CHANNEL 1 (YELLOW): OUTA CHANNEL 3 (BLUE): CS CHANNEL 2 (RED): OUTB CHANNEL 4 (GREEN): IOUT
where t is the charging period in ms and C is the value of the soft-start capacitor in F. The soft-start duration experienced by the power supply will be less than or equal to this value, depending on when the feedback loop takes control. The soft-start voltage is clamped to 4.50V with an overall tolerance of 2%. It is suitable for use as a "soft-started" reference provided the current draw is kept well below the 70A charging current. The outputs may be inhibited by using the SS pin as a disable input. Pulling SS below 0.25V forces all outputs low. An open collector/drain configuration may be used to couple the disable signal to the SS pin.
FIGURE 5. CS INPUT vs IOUT
Figure 5 shows the relationship between the CS signal and IOUT under steady state conditions. IOUT is 4x the average of CS. Figure 6 shows the dynamic behavior of the current averaging circuitry when CS is modulated by an external sine wave. Notice IOUT is updated by the sample and hold circuitry at the termination of the active output pulse.
Gate Drive
The ISL6742 outputs are capable of sourcing and sinking 10mA (at rated VOH, VOL) and are intended to be used in conjunction with integrated FET drivers or discrete bipolar totem pole drivers. The typical ON-resistance of the outputs is 50.
Overcurrent Operation
Two overcurrent protection mechanisms are available to the power supply designer. The first method is cycle-by-cycle peak overcurrent protection, which provides fast response. The second method is a slower, averaging method, which produces constant or "brick-wall" current limit behavior. If voltage-mode control is used, the average overcurrent protection also maintains flux balance in the transformer by maintaining duty cycle symmetry between half-cycles.
CHANNEL 1 (YELLOW): OUTA CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTB CHANNEL 4 (GREEN): IOUT
FIGURE 6. DYNAMIC BEHAVIOR OF CS vs IOUT
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The average current signal on IOUT remains accurate provided that the output inductor current is continuous (CCM operation). Once the inductor current becomes discontinuous (DCM operation), IOUT represents 1/2 the peak inductor current rather than the average current. This occurs because the sample and hold circuitry is active only during the on-time of the switching cycle. It is unable to detect when the inductor current reaches zero during the off-time. If average overcurrent limit is desired, IOUT may be used with the available error amplifier of the ISL6742. Typically, IOUT is divided down and filtered as required to achieve the desired amplitude. The resulting signal is input to the current error amplifier (IEA). The IEA is similar to the voltage EA found in most PWM controllers, except it cannot source current. Instead, VERR has a separate internal 1mA pull-up current source. Configure the IEA as an integrating (Type I) amplifier using the internal 0.6V reference. The voltage applied at FB is integrated against the 0.6V reference. The resulting signal, VERR, is applied to the PWM comparator where it is compared to the sawtooth voltage on RAMP. If FB is less than 0.6V, the IEA will be open loop (can't source current), VERR will be at a level determined by the voltage loop, and the duty cycle is unaffected. As the output load increases, IOUT will increase, and the voltage applied to FB will increase until it reaches 0.6V. At this point the IEA will reduce VERR as required to maintain the output current at the level that corresponds to the 0.6V reference. When the output current again drops below the average current limit threshold, the IEA returns to an open loop condition, and the duty cycle is again controlled by the voltage loop. The average current control loop behaves much the same as the voltage control loop found in typical power supplies except it regulates current rather than voltage. The EA available on the ISL6742 may also be used as the voltage EA for the voltage feedback control loop rather than the current EA as described previously. An external op amp may be used as either the current or voltage EA providing the circuit is not allowed to source current into VERR. The external EA must only sink current, which may be accomplished by adding a diode in series with its output. The 4x gain of the sample and hold buffer allows a range of 150mV to 1000mV peak on the CS signal, depending on the resistor divider placed on IOUT. The overall bandwidth of the average current loop is determined by the integrating current EA compensation and the divider on IOUT.
150mV TO 1000mV
1
ISL6742
2 VERR C10 3 4 5 FB 0.6V + 6 S&H 7 CS 4x 8 IOUT R6 R5
1 6 1 5 1 4 1 3 1 2 1 1 1 0 9
R4
FIGURE 7. AVERAGE OVERCURRENT IMPLEMENTATION
The current EA crossover frequency, assuming R6 >> (R4||R5), is expressed in Equation 7:
1 f CO = ---------------------------------2 R6 C10 Hz (EQ. 7)
where fCO is the crossover frequency. A capacitor in parallel with R4 may be used to provide a double-pole roll-off. The average current loop bandwidth is normally set to be much less than the switching frequency, typically less than 5kHz and often as slow as a few hundred hertz or less. This is especially useful if the application experiences large surges. The average current loop can be set to the steady state overcurrent threshold and have a time response that is longer than the required transient. The peak current limit can be set higher than the expected transient so that it does not interfere with the transient, but still protects for short-term larger faults. In essence, a 2-stage overcurrent response is possible. The peak overcurrent behavior is similar to most other PWM controllers. If the peak current exceeds 1V, the active output pulse is terminated immediately. If voltage-mode control is used in a bridge topology, it should be noted that peak current limit results in inherently unstable operation. DC blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. The average overcurrent circuitry prevents this behavior by maintaining symmetric duty cycles for each half-cycle. If the average current limit circuitry is not used, a latching overcurrent shutdown method using external components is recommended. The CS to output propagation delay is increased by the leading edge blanking (LEB) interval. The effective delay is the sum of the two delays and is 130ns maximum.
Voltage Feed-Forward Operation
Voltage feed-forward is a technique used to regulate the output voltage for changes in input voltage without the
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intervention of the control loop. Voltage feed-forward is often implemented in voltage-mode control loops, but is redundant and unnecessary in peak current-mode control loops. Voltage feed-forward operates by modulating the sawtooth ramp in direct proportion to the input voltage. Figure 8 demonstrates the concept.
VIN
Referring to Figure 9, the charging time of the ramp capacitor is expressed in Equation 8:
V RAMP ( PEAK ) t = - R3 C7 ln 1 - --------------------------------------- V IN ( MIN ) s (EQ. 8)
For optimum performance, the maximum value of the capacitor should be limited to 10nF. The DC current through the resistor should be limited to 3mA. For example, if the oscillator frequency is 400kHz, the minimum input voltage is 300V and a 4.7nF ramp capacitor is selected. The value of the resistor can be determined by rearranging Equation 8.
- 2.5 10 -t R3 = ------------------------------------------------------------------------- = ------------------------------------------------------------9 1 V RAMP ( PEAK ) 4.7 10 ln 1 - --------- C7 ln 1 - --------------------------------------- 300 V IN ( MIN ) ) = 159 k (EQ. 9)
-6
ERROR VOLTAGE RAMP
CT
OUTA, OUTB
where t is equal to the oscillator period minus the deadtime. If the deadtime is short relative to the oscillator period, it can be ignored for this calculation. When implemented, the voltage feed-forward feature also provides a volt-second clamp on the transformer. The maximum duty cycle is determined by the lesser of the oscillator period or the RAMP charge time. As the input voltage increases, the RAMP charge time decreases, limiting the duty cycle proportionately. If feed-forward operation is not desired, the RC network may be connected to VREF or a buffered CT signal rather than the input voltage. Regardless, a sawtooth waveform must be generated on RAMP as it is required for proper PWM operation.
FIGURE 8. VOLTAGE FEED FORWARD BEHAVIOR
Input voltage feed-forward may be implemented using the RAMP input. An RC network connected between the input voltage and ground, as shown in Figure 9, generates a voltage ramp proportional to the amplitude of the source voltage. At the termination of the active output pulse, RAMP is discharged to ground so that a repetitive sawtooth waveform is created. The RAMP waveform is compared to the VERR voltage to determine duty cycle. The selection of the RC components depends upon the desired input voltage operating range and the frequency of the oscillator. In typical applications, the RC components are selected so that the ramp amplitude reaches 1V at minimum input voltage within the duration of one half-cycle.
VIN 1 2 R3 3 4 5 6 RAMP 7 C7 8 ISL6742 16 15 14 13 12 11 10 GND 9
Implementing Synchronization
Synchronization to an external clock signal may be accomplished in the same manner as many PWM controllers that do not have a separate synchronization input. By injecting a short pulse across a small resistor in series with the timing capacitor, the oscillator sawtooth waveform may be terminated prematurely. The injected pulse width should be narrower than the sawtooth discharge duration.
1 2 3 4 CT CT 5 6 7 8 RS ISL6742 16 15 14 13 12 11 10 GND 9
FIGURE 9. VOLTAGE FEED-FORWARD CONTROL
FIGURE 10. SYNCHRONIZATION TO AN EXTERNAL CLOCK
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ISL6742
Synchronous Rectifier Outputs and Control
The ISL6742 provides double-ended PWM outputs, OUTA and OUTB, and synchronous rectifier (SR) outputs, OUTAN and OUTBN. The SR outputs are the complements of the PWM outputs. It should be noted that complemented outputs are used in conjunction with the opposite PWM output, i.e. OUTA and OUTBN are paired together and OUTB and OUTAN are paired together. Referring to Figure 11, the SRs alternate between being both on during the free-wheeling portion of the cycle (OUTA/OUTB off), and one or the other being off when OUTA or OUTB is on. If OUTA is on, its corresponding SR must also be on, indicating that OUTBN is the correct SR control signal. Likewise, if OUTB is on, its corresponding SR must also be on, indicating that OUTAN is the correct SR control signal.
CT
OUTA
OUTB
OUTAN (SR1) OUTBN (SR2)
FIGURE 12. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED, 0V < VADJ < 2.425V
CT
OUTA
CT
OUTB
OUTA
OUTAN (SR1)
OUTB
OUTBN (SR2)
OUTAN (SR1)
FIGURE 11. BASIC WAVEFORM TIMING
A useful feature of the ISL6742 is the ability to vary the phase relationship between the PWM outputs (OUTA, OUTB) and their complements (OUTAN, OUTBN) by 300ns. This feature allows the designer to compensate for differences in the signal propagation delays between the PWM FETs and the SR FETs. A voltage applied to VADJ controls the phase relationship. Figures 12 and 13 demonstrate the delay relationships.
OUTBN (SR2)
FIGURE 13. WAVEFORM TIMING WITH SR OUTPUTS DELAYED, 2.575V < VADJ < 5.00V
Setting VADJ to VREF/2 results in no delay on any output. The no delay voltage has a 75mV tolerance window. Control voltages below the VREF/2 zero delay threshold cause the PWM outputs, OUTA/OUTB, to be delayed. Control voltages greater than the VREF/2 zero delay threshold cause the SR outputs, OUTAN/OUTBN, to be delayed. It should be noted that when the PWM outputs, OUTA/OUTB, are delayed, the CS to output propagation delay is increased by the amount of the added delay. The delay feature is provided to compensate for mismatched propagation delays between the PWM and SR outputs as may be experienced when one set of signals crosses the primary-secondary isolation boundary. If required, individual output pulses may be stretched or compressed as required using external resistors, capacitors, and diodes.
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ISL6742
Slope Compensation
Peak current-mode control requires slope compensation to improve noise immunity, particularly at lighter loads, and to prevent current loop instability, particularly for duty cycles greater than 50%. Slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation, is expressed in Equation 10:
1 F m = -------------Sn Sn (EQ. 10)
Vn can be solved for in terms of input voltage, current transducer components, and output inductance yielding Equation 16:
t SW V R CS N O S1 -V e = --------------------------------------- ------- -- + D - 0.5 N CT L O NP V (EQ. 16)
where RCS is the current sense burden resistor, NCT is the current transformer turns ratio, LO is the output inductance, VO is the output voltage, and NS and NP are the secondary and primary turns, respectively. The current sense signal, which represents the inductor current after it has been reflected through the isolation and current sense transformers, and passed through the current sense burden resistor, is expressed in Equation 17:
N S R CS D t SW NS V CS = ------------------------ I O + ------------------ V IN ------- - V O 2L O NP N P N CT V (EQ. 17)
where Sn is the slope of the sawtooth signal and tSW is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes Equation 11:
1 1 F m = ----------------------------------- = ------------------------m c S n t SW ( S n + S e )t SW (EQ. 11)
where VCS is the voltage across the current sense resistor and IO is the output current at current limit. Since the peak current limit threshold is 1V, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold.
V e + V CS = 1 (EQ. 18)
where Se is slope of the external ramp and:
Se m c = 1 + -----Sn (EQ. 12)
The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at half the oscillator frequency. The double-pole will be critically damped if the Q-factor is set to 1, over-damped for Q > 1, and under-damped for Q < 1. An under-damped condition may result in current loop instability.
1 Q = ------------------------------------------------ ( m c ( 1 - D ) - 0.5 ) (EQ. 13)
Substituting Equations 16 and 17 into Equation 18 and solving for RCS yields Equation 19:
N P N CT 1 R CS = ----------------------- --------------------------------------------------NS VO 1 + D -I O + ------- t SW -- -- 2 L
O
(EQ. 19)
where D is the percent of on-time during a half cycle (half period duty cycle). Setting Q = 1 and solving for Se yields Equation 14:
1 1 S e = S n -- + 0.5 ------------ - 1 1-D (EQ. 14)
For simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining the amount of external ramp to add. Magnetizing inductance provides a degree of slope compensation and reduces the amount of external ramp required. The magnetizing inductance adds primary current in excess of what is reflected from the inductor current in the secondary.
V IN Dt SW I P = ----------------------------Lm A (EQ. 20)
Since Sn and Se are the on-time slopes of the current ramp and the external ramp, respectively, they can be multiplied by tON to obtain the voltage change that occurs during tON.
1 1 V e = V n -- + 0.5 ------------ - 1 1-D (EQ. 15)
where VIN is the input voltage that corresponds to the duty cycle D and Lm is the primary magnetizing inductance. The effect of the magnetizing current at the current sense resistor, RCS, is expressed in Equation 21:
I P R CS V CS = ------------------------N CT V (EQ. 21)
where Vn is the change in the current feedback signal during the on time and Ve is the voltage that must be added by the external ramp.
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ISL6742
If VCS is greater than or equal to Ve, then no additional slope compensation is needed and RCS becomes Equation 22:
N CT R CS = --------------------------------------------------------------------------------------------------------------------------------NS Dt SW NS V IN Dt SW ------- I O + -------------- V IN ------- - V O + ----------------------------NP 2L O NP Lm (EQ. 22)
Example: VIN = 280V VO = 12V LO = 2.0H NP/NS = 20 Lm = 2mH IO = 55A Oscillator Frequency, FSW = 400kHz Duty Cycle, D = 85.7% NCT = 50 R6 = 499 Solve for the current sense resistor, RCS, using Equation 19. RCS = 15.1. Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 16. Ve = 153mV Next, determine the effect of the magnetizing current from Equation 21. VCS = 91mV Using Equation 24, solve for the summing resistor, R9, from CT to CS.
If VCS is less than Ve, then Equation 19 is still valid for the value of RCS, but the amount of slope compensation added by the external ramp must be reduced by VCS. Adding slope compensation is accomplished in the ISL6742 using an external buffer and the CT signal. A typical application sums the buffered CT signal with the current sense feedback and applies the result to the CS pin as shown in Figure 14.
1 2 3 4
VREF ISL6742 CT
16 15 14 13 12 11
R9
5 6 7
CS
10 9
R6
8
RCS
C4
CT
R9 = 13.2k Determine the new value of RCS, R'CS, using Equation 25. R'CS = 15.7
FIGURE 14. ADDING SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter (R6 and C4) placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition.
2D R6V e - V CS = --------------------R6 + R9 V (EQ. 23)
Additional slope compensation may be considered for design margin. This discussion determines the minimum external ramp that is required. The buffer transistor used to create the external ramp from CT should have a sufficiently high gain (>200) so as to minimize the required base current. Whatever base current is required reduces the charging current into CT and will reduce the oscillator frequency.
Rearranging to solve for R9 yields:
( 2D - V e + V CS ) R6 R9 = -----------------------------------------------------------V e - V CS (EQ. 24)
Parallel Operation
Parallel operation of converters using the ISL6742 may be accomplished using the average current signal, IOUT. IOUT provides a very accurate representation of the output current and may be used for active current sharing with many sharing techniques commonly used including master-slave and average current sharing methods. Since IOUT represents the average inductor current (CCM operation), sharing errors introduced by techniques using peak inductor current are reduced. In particular, the current sharing error introduced by mismatched switching frequencies is eliminated.
The value of RCS determined in Equation 19 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 17. The divider created by R6 and R9 makes this necessary.
R6 + R9 R CS = --------------------- R CS R9 (EQ. 25)
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ISL6742
Figure 15 illustrates a master-slave current sharing method.
VOLTAGE ERROR AMPLIFIER INVERTING (-) INPUT BIAS U1 1 16 2 ISL6742 15 3 VDD 14 4 13 5 12 6 11 S&H 7 CS 10 4x 8 IOUT 9 R1 + U2A R3
distribution drops between the power supply outputs and the remote sensing location. The current limit circuit must limit the voltage change to less than the output overvoltage threshold or an overvoltage condition can be induced. Amplifier U2A sets the scaling factor from IOUT to IShare and increases the current sourcing capability of IShare. U2B is a low bandwidth amplifier that sets the frequency response and gain of the current share circuitry. The current share bandwidth must be much lower than the voltage feedback loop bandwidth to ensure overall stability. The gain is set by R1 and R5, and the bandwidth by R5 and C1. The disconnect in series with IShare may be omitted for power systems that do not require fault isolation. The disconnect switch is normally implemented with MOSFET or JFET devices.
R2 (>>R1) C1 R5 (>>R1) U2B +
VOUT
OUTPUT VOLTAGE FEEDBACK DIVIDER
Q1
R7
R4 (>>R3)
R6
Average Current Mode Control
The average current signal produced on IOUT may also be used for average current mode control rather than peak current mode control. There are many advantages to average current mode control, most notably, improved noise immunity and greater design flexibility of the current feedback loop compensation. Figure 16 portrays the concept.
C2 R3 IOUT R2 R4 VERR U2 + CURRENT ERROR AMPLIFIER OFFSET U1 + REF VOLTAGE ERROR AMPLIFIER Rb VOUT C1 R1
ISHARE DISCONNECT IF P/S FAILS OR IS TURNED OFF
FIGURE 15. MASTER-SLAVE CURRENT SHARING USING AVERAGE CURRENT
In parallel and redundant applications, the IShare signals from each power supply are connected together. Each power supply produces a voltage proportional to its average output current on IOUT, and through limiting resistor R3, on IShare. The unit with the highest IShare signal (and highest output current) sources current onto the IShare Bus, and is identified as the master unit. The units with lower IShare signals do not source current onto IShare, and are identified as slave units. Each slave unit compares the master's IShare signal with its own, and if there is sufficient difference, turns Q1 on, which pulls down on the feedback voltage. Reducing the feedback voltage causes the output voltage to appear low; the feedback loop compensates by increasing the output voltage, and the output current increases. Each slave unit will increase its output voltage until its output current is nearly equal to that of the master. The difference between the master's output current and that of a slave unit is set by R1 and R2. Some difference is required to prevent undesirable switching of master and slave roles. This difference also prevents operation of the current sharing circuitry when a power supply is operating stand alone. The maximum output voltage that a slave can induce in its output is controlled by R6 and the output voltage feedback divider. Typically, the maximum allowed output voltage increase is limited to a few percent, but must be greater than the tolerance of the feedback and reference components and any distribution drops between units. If remote sensing is used, the adjustment range must also include the difference in
FIGURE 16. AVERAGE CURRENT MODE CONTROL
Instead of being compared to a peak current sense signal as it would be in a peak current mode control configuration, the voltage amplifier output is integrated against the average output current. The voltage loop compensation and the current loop compensation may be adjusted independently. The voltage error amplifier programs the average output current of the supply, and its maximum output level determines the maximum output current. Either IOUT or the voltage EA output must be scaled appropriately to achieve the desired current limit setpoint. The offset voltage shown in Figure 16 must be provided to compensate for input offset voltage of the current amplifier to ensure that zero duty cycle operation is achievable. Depending on the performance requirements of the control loop, compensation networks other than shown may be required.
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ISL6742
Fault Conditions
A fault condition occurs if VREF or VDD fall below their undervoltage lockout (UVLO) thresholds or if the thermal protection is triggered. When a fault is detected, the soft-start capacitor is quickly discharged, and the outputs are disabled low. When the fault condition clears and the soft-start voltage is below the reset threshold, a soft-start cycle begins. An overcurrent condition is not considered a fault and does not result in a shutdown.
Thermal Protection
Internal die over temperature protection is provided. An integrated temperature sensor protects the device should the junction temperature exceed +140C. There is approximately +15C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD and VREF should be bypassed directly to GND with good high frequency capacitance.
References
[1] Ridley, R., "A New Continuous-Time Model for Current Mode Control", IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991.
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FN9183.2 October 31, 2008
ISL6742 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA E -B1 2 3 0.25 0.010 h x 45 L GAUGE PLANE H 0.25(0.010) M BM
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1
SEATING PLANE -AD -CA
MILLIMETERS MIN 1.55 0.102 1.40 0.20 0.191 4.80 3.81 MAX 1.73 0.249 1.55 0.31 0.249 4.98 3.99 NOTES 9 3 4 5 6 7 8 Rev. 2 6/04
MIN 0.061 0.004 0.055 0.008 0.0075 0.189 0.150
MAX 0.068 0.0098 0.061 0.012 0.0098 0.196 0.157
A2 B C D
A1 0.10(0.004) A2 C
E e H h L
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.230 0.010 0.016 16 0 8 0.244 0.016 0.035
0.635 BSC 5.84 0.25 0.41 16 0 6.20 0.41 0.89
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN9183.2 October 31, 2008

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